This invention relates to a lateral high-breakdown-voltage transistor.
The lateral high-breakdown-voltage MOS transistor is a type of a power MOS transistor, which is switched on when a voltage ranging from several tens to several hundreds volts is applied thereto.
FIG. 13A is an enlarged plan view illustrating part of the planar pattern of a conventional lateral high-breakdown-voltage MOS transistor. FIG. 13B is a sectional view taken along line 13B—13B of FIG. 13A. In FIG. 13A, the gate electrode of the transistor is omitted.
As shown in FIGS. 13A and 13B, a low-concentration n− drain region 102 is formed in a low-concentration p− silicon substrate 101, and a high-concentration n+ source region 103 is formed therein, separated from the drain region 102. A gate electrode 105 is formed on that portion of the substrate 101, which is located between the drain and source regions 102 and 103, i.e. on a channel 104, such that the electrode 105 is electrically isolated from the substrate 101.
An n+ drain contact region 106 having a higher impurity concentration than the drain region 102 is formed in the drain region 102. The drain contact region 106 is sufficiently separated from the channel 104 by means of a field insulating film 108 formed on the substrate 101. The field insulating film 108 is made of, for example, silicon dioxide, and formed by the LOCOS (Local Oxidation of Silicon) technique, or STI (Shallow Trench Isolation) technique, etc. Further, high-concentration p+ substrate contact regions 107 are formed in the substrate 101 in contact with the source region 103.
An interlayer insulating film 109 made of, for example, silicon dioxide is formed on the field insulating film 108 and on those portions of the substrate 101, in which the aforementioned semiconductor regions are formed. The interlayer insulating film 109 has a contact hole 110 that exposes the drain contact region 106 therethrough, and a contact hole 111 that exposes the source region 103 and the substrate contact regions 107 therethrough. Drain wiring 112 is provided on the interlayer insulating film 109 such that it comes into contact with the drain contact region 106 via the contact hole 110. Similarly, source wiring 113 is provided on the interlayer insulating film 109 such that it comes into contact with the source region 103 and the substrate contact regions 107 via the contact hole 111. The drain wiring 112 is electrically connected to the drain region 102 via the drain contact region 106. In FIG. 13A, reference numeral 116 denotes a contact surface between the drain wiring 112 and the drain contact region 106. The source wiring 113 is electrically connected to the source region 103, and also to the substrate 101 via the substrate contact regions 107. Further, in FIG. 13A reference numeral 115 denotes a contact surface between the source wiring 113 and the source region 103, the substrate contact regions 107.
Since, in the lateral high-breakdown-voltage MOS transistor, the drain and source regions 102 and 103 exist at the same level as shown in FIG. 13A, a lateral parasitic bipolar transistor exists which uses the drain region 102, the substrate 101 and the source region 103 as a collector, a base and an emitter, respectively. When the lateral parasitic bipolar transistor is turned on, it adversely affects the operation of the MOS transistor. The lateral parasitic bipolar transistor is turned on, for example, in the following situation.
When the gate is turned on and the voltage at the drain is increased, avalanche breakdown starts at a curved surface 114 of the drain contact region 106, whereby a hole current flows toward the substrate 101. This hole current flows below the source region 103 to the substrate contact regions 107, and then, usually, to the source wiring 113 via substrate contact regions 107.
When the voltage at the drain is further increased, the level of the avalanche breakdown increases to thereby increase the hole current. As the hole current increases, a high voltage is generated due to the resistance of a portion of the substrate 101 below the source region 103. Accordingly, forwardly biasing of the PN junction between the substrate 101 and the source region 103 occurs, thereby turning on the lateral parasitic bipolar transistor. When the lateral parasitic bipolar transistor is turned on, control using the gate cannot be executed, resulting in breakdown of the lateral high-breakdown-voltage MOS transistor.